Field
The disclosed technology relates to the field of switching circuits impacted by charge injection, as encountered in digital transmitters, high speed digital to analog converters (DACs) and the like.
Description of the Related Technology
Nanoscale CMOS has brought many high speed applications to the consumer thanks to the computing power that can be squeezed into modern signal processors. Unfortunately, the intrinsic analog properties of CMOS transistors do not follow the improvements of their digital counterparts. CMOS transistor parameters including output impedance, supply versus threshold ratio and intrinsic gain typically worsen with the advance of the CMOS technological nodes.
One example of an important application field relates to digital radio transmitters. Modern communication schemes impose tough requirements on radio transmitters. Transmitters operating at RF have to combine hard requirements such as RF bandwidth, linearity and out-of-band noise while maintaining high efficiency. As a result, porting an analog RF transmitter from one technological node to another is complicated and therefore slow and costly. Therefore, transmitters need to have the least possible analog circuitry. In addition, it is desirable for radio transmitters to be easily scalable with the advancement of CMOS technologies.
To address the problem of analog RF transmitters, a new family of RF transmitters, digital transmitters (also referred to as RF-DACs or Direct Digital RF Modulators, DDRM), has been adopted. The digital transmitters feature predominantly digital circuitry which is better suited for advanced CMOS technology and which scales much better with various CMOS technological nodes. In contrast to their analog counterpart, the performance of digital transmitters intrinsically improves with the scaling of CMOS technology.
The first digital transmitters were based on a polar architecture, in which a phase modulated local oscillator (LO) signal is fed to a multitude of DDRM units and amplitude modulation is performed by enabling or disabling (switching on or off) these DDRM unit amplifiers and then combining their output power to form a modulated RF analog signal. Later, Cartesian DDRM architectures consisting of two such digital amplitude modulators, for modulating the in-phase (I) and the quadrature (Q) signals with the respective LO phasess. The outputs of these two digital amplitude modulators are summed before being fed to the antenna for transmission.
An RF DAC is created by summing the outputs of a multitude of switched current sources. In a traditional high speed DAC a differential operation is typically applied and the current of the unit current source is switched to either the positive or the negative side in order to keep the current in the current source constant. To achieve a low instantaneous amplitude during modulation at the RFDAC output a number of unit cells (current sources) are effectively turned off in order to avoid power waste and to keep a high efficiency of the transmitter.
In the paper “A linear 28 nm CMOS digital transmitter with 2×12 bit up to LO baseband sampling and—58 dBc C-IM3” (M. Ingels et al., Eur. Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014, pp. 379-382) a current source based DDRM is disclosed in which a very high output impedance is targeted, even at maximal code and high output power. Each unit DDRM cell includes a current source transistor, which allows achieving operation with linear response. The output current of the DDRM is given by the number of active units cells multiplied by the unit current of the active cells.
FIG. 1 illustrates an implementation of a unit cell. Switch transistor SW1 is connected in series to transistor M1, which determines and delivers the current provided by the cell. M1 is biased by the voltage Vb at its gate and acts as a current source. The current provided by this current cell can be turned off by the MOS transistor SW1, which acts as a switch, and which has a digital signal at its input. This signal will typically occur at a very high speed. In the paper this switching occurs at an (intermittent) LO speed. Switching on or off SW1 enables or disables the conversion cell. When SW1 is enabled, the current source transistor M1 generates an analog signal at the output of the cell. In other words, the switch transistor SW1 determines whether a current is flowing through the current source transistor M1.
The value of that current is mainly determined by the bias voltage Vb applied at the gate terminal of M1 and the dimensions of transistor M1. By adjusting the bias voltage Vb, the value of the current flowing, i.e., the analog signal amplitude, can be adjusted. Consequently, digital modulation is achieved by turning on more or less of the cells. Vb controls the level of the digitally modulated signal. It can be seen as controlling the digital transmitter gain. The switch transistor resistance results in some extra power dissipation when a current is flowing through the activated unit cell. Its resistance value should thus be chosen low enough to limit this dissipation. As the bias voltage of transistor M1 and its dimensions determine the current of the active unit cells, it determines the transmitter output power. While the current in the given unit cell is constant when the cell is in operation (and thus contributing to the modulation), the current may be adjusted to control the RMS output power of the transmitter and thus its gain.
Switching activity of the switch SW1 in an RF-DAC unit positioned as in FIG. 1 causes the source voltage of the current source transistor M1 to vary rapidly and inject charge into the bias node of the current source through the transistor's gate-source capacitance. This affects the bias voltage of the current source in the unit and the current provided by the current source. As a result, the current provided by the current source transistor is no longer the ideal nominal value and the sum of the currents of all the active unit cells is not the correct expected value.
When the bias voltage is disturbed by charge injection, it starts settling back to its nominal value right after the disturbance, but it does not reach its nominal value within one switching cycle (see FIG. 2). This voltage settling on the bias node is determined by the time constant of that bias node, which is typically much longer than the switching speed of the unit cells. The time constant of the bias node is defined by the output impedance at the bias node and the decoupling capacitor Cd, which in turn form a low-pass filter. Indeed, the time constant of the current cell is typically in the frequency range of the baseband signal (MHz range). The time constant is determined by the output impedance of the bias circuit, which may be a simple diode or a more elaborate circuit, and the decoupling capacitor, while the switching speed of the units typically occurs at the rhythm of the output RF frequency (GHz range).
When a second charge injection occurs at the next switching event, the bias voltage is still settling and further deviates from its nominal value, as it already deviated from the first occurrence and was not yet able yet to regain its nominal state. If unit cells are continuously active, the bias voltage eventually settles to a certain equilibrium point (as the drive towards the nominal value gets stronger as the bias voltage deviates more). However, in a DDRM the activity of the various units depends on the baseband data and activity periods alternate with periods of inactivity. Therefore, periods of switching activity alternate with cycles without switching activity. As a result, the current provided by a unit cell after a long inactivity is different from the unit cell current provided after a period of more intense switching activity (in the first case it is closer to the nominal value, in the second case it is further off).
As the switching activity in a DDRM depends on the baseband data, the current provided by the unit cells depends on the ‘history’ of the baseband data. This is a memory effect. The current of the unit cells depends on the data applied to the cell before. This results in distortion of the output signal of the DDRM and is difficult to predistort. In a DDRM it is even tougher as the bias voltage is typically shared between many or all the DDRM units. As a result, the bias voltage for a given unit is affected by the activity in other cells, which makes the effect and the eventual predistortion even tougher. Furthermore, the partitioning of the units into binary and thermometer coded groups of units add even more to the distortion (as there is no simple relation with for example the signal amplitude and the amount of charge injection).
In order to avoid the need for predistortion, it is essential to keep the output impedance variation small relative to the load impedance. Therefore, the unit cell further includes an additional transistor M3 in cascode to the current source transistor M1, as illustrated in FIG. 3. As the output impedance of the DDRM can be considered in parallel with the load to the DDRM, the actual load seen by the DDRM is a parallel circuit of the effective load and its own output impedance. The higher this output impedance, the lower its contribution, and the lower the impact of variations (due to the modulation) of this output impedance. Consequently, the increased output impedance further improves the linear operation of the DDRM so that pre-distortion is not (or at least much less) needed. In an RF DAC the transistor M2 in cascode is typically a thick oxide device which protects the fast thin oxide core from a large output swing.
In the implementations shown in FIG. 1 and FIG. 3, the switch SW1 is placed below (i.e. the drain terminal of the switch is connected to the source terminal of the current source transistor) the current source in order to maximize the overdrive voltage of the switch when it is turned on and so to reduce its on-resistance. As the unit amplifier is turned on and off, the voltage at the source terminal of the current source moves up and down at the rhythm of the switching, with a voltage swing which is close to the overdrive voltage of the current source transistor M1. As the source terminal and the gate of the current source transistor M1 are coupled through its gate-source capacitance, a charge is injected from the source node to the gate node at each edge of the swinging voltage. This creates a voltage spike at the gate of the current source transistor M1, whose amplitude depends on the size of the gate-source capacitance, on the decoupling capacitor used to decouple the gate node and on the source impedance of the circuit providing the bias voltage to the current source. The latter circuit can be as simple as a diode connected transistor followed by a low-pass filter, but it may be more complex. The low-pass filter may consist of a single decoupling cap together with the non-zero output impedance of the (diode) source and is typically provided to stabilize the bias voltage of the current source. After each voltage spike, the bias voltage tends to evolve towards the nominal value, with a settling time determined by the time constant of the low-pass filter.
Unfortunately, as the rising and falling edges at the source terminal of the current source transistor are not equal and as the settling of the bias node is typically much slower than the switching frequency of the switch, the amounts of charge injected onto and extracted from the decoupling capacitance within one switching sequence are not equal and some residual charge will persist. This residual charge is compensated by the bias source, but due to its limited bandwidth, it may not occur within one switching clock cycle (see FIG. 2). As a result, when the unit amplifier is switched on a second time, the residual charge, which is still present, causes a slight difference in the bias voltage of the current source and the current at the output will be slightly different. This eventually results in distortion at the RF-DAC output. Moreover, as the residual charge is built up from the subsequent active cycles and as the recovery takes multiple switching cycles, the resulting distortion in a given unit amplifier is dependent on the past activity of this unit amplifier. In other words, there are memory effects in the distortion. The resulting distortion is even more significant when a common bias and/or decoupling is used for multiple unit amplifiers, as the charge injection of one amplifier disturbs the other amplifiers. This is typically the case in a DDRM. However, as predistortion algorithms having to deal with memory effects are complex and limited in effectivity, especially when there is interaction between the various units. this effect should be avoided in the design already.
US PG Publication No. US2010/0254490 discloses various implementations of a mixer for a high gain range transmitter. A differential circuit is proposed to implement the mixer. Due to the switching activity, charge is injected through the gate-drain capacitances of the transistors at the local oscillator inputs. In order to compensate for this charge injection additional cross-coupled transistors are provided acting as capacitances. In this way the charge injection from the gate-drain capacitance of a first switching transistor receiving one LO phase can be cancelled through the gate capacitance of the extra cross-coupled transistor used as a capacitor and receiving the opposite LO phase signal and vice versa. In this way the direct charge injection into the signal path due to the switching activity in the LO signal is cancelled.
Hence, there is a need for modifying the RF DAC unit cell so that charge injection is reduced and thus any need for providing complex predistortion is avoided.